Allwinner /D1H /UART[0] /MSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (no_change)dcts 0 (no_change)ddsr 0 (no_change)teri 0 (no_change)ddcd 0 (deasserted)cts 0 (deasserted)dsr 0 (deasserted)ri 0 (deasserted)dcd

ri=deasserted, dsr=deasserted, cts=deasserted, dcd=deasserted, teri=no_change, ddsr=no_change, ddcd=no_change, dcts=no_change

Description

UART Modem Status Register

Fields

dcts

Delta Clear to Send

0 (no_change): undefined

1 (change): undefined

ddsr

Delta Data Set Ready

0 (no_change): undefined

1 (change): undefined

teri

Trailing Edge Ring Indicator

0 (no_change): undefined

1 (change): undefined

ddcd

Delta Data Carrier Detect

0 (no_change): undefined

1 (change): undefined

cts

Line State of Clear To Send

0 (deasserted): undefined

1 (asserted): undefined

dsr

Line State of Data Set Ready

0 (deasserted): undefined

1 (asserted): undefined

ri

Line State of Ring Indicator

0 (deasserted): undefined

1 (asserted): undefined

dcd

Line State of Data Carrier Detect

0 (deasserted): undefined

1 (asserted): undefined

Links

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